Comp Sci - Topic 2 and 6

Maximizing the 24 slots of hex bits available

D6

4D

25

Arithmetic Logic Unit, used for handling arithmetic operations and basic input/output logic operations

A character set which involves all Latin letters

Programs are grouped together based on dependencies then executed sequentially

Less resource intensive but less optimal because of Latency

Optimal behavior but resource intensive

Faster, efficient in relation to using a single cpu/single core system

Direct access [HDD/SSID] and Sequential access

CPU time occupied by process without waiting for input/output

Holds the information from the RAM that is most actively used and accessed most frequently. Most relevant types of cache rn are L1 and L2. 

L1 is placed on the CPU and L2 is placed between the 1⁰ and 2⁰

Current Instruction Register: Stores the instruction currently being decoded

the person/institution funding the product

a process where the memory manager rearranges the memory space to create larger blocks of contiguous memory. Excessive compaction can lead to checkerboaring

01011001

2D

4F

Control Unit, it’s what retrieves the instructions from the 1⁰ and handles its execution

Dynamic Ram:

• Cheaper

• Requires constant refreshing to keep data useable

• Data leaks

• Memory capacity»

• HL [DDR, double data rate, data is transferred at the rise and fall of the clock]

When two or more processes are blocked, needing to access shared resources in a specific order

The instruction goes from the MDR to the CIR
CU decodes the instruction, sees whether or not it can pass
If it’s passable CU sends a decoded version to the ALU

The part of the computer that performs instructions based on input and output

It hides the complexities of functions. It’s the process of moving out idle applications from 1⁰ to the 2⁰ (temporarily) to make space for incoming applications. It’s returned to primary memory as needed and stored in units called pages.

ROM cannot be written to, RAM can
ROM holds the Basic [Input/Output] System, RAM holds the programs running and data used
ROM is much smaller than RAM
ROM is non-volatile, RAM is volatile

refreshing

thrashing

Fragmentation

ALU performs arithmetic or logical operation as instructed. The latest result is stored in the accumulator

• Program Counter (PC) sends address of the next instruction to Memory Address Register

• Memory Address Bus (MAB) sends this address to the RAM

• The memory unit uses the address to locate the instruction in RAM.

• The instruction is fetched from RAM and placed on the Memory Data Bus (MDB).

• The MDR captures the fetched instruction.

A numerical notation using base 16

Make it the capacity of a byte (8 bits long), split it into 2, then use the table for conversion. 

Divide by two, note 1 for each odd number and note 0 for each even number. from bottom to top put together the string of binary.  

Convert to binary, then turn the binary into byte form and break it in half

Each Hex number seperately, find each letter/number equivalent on the table, put them together

When the periphreal device issues an error/interrupt signal to the processor to signify change in status

Files will lose quality when it is compressed

Standing for Media Access Control Address, it's a unqiue 12-character alphanumeric attribute that is used to identify individual electronic devices on a network. It's built in and cannot be removed (anymore)

Memory Address Register:

Stores the memory address from which data will be fetched

Memory Data Register: Holds the data fetched from during the cycle

When an application is quit but the allocated memory is still being used

Occurs in place of paging, when there isn’t a present block. Storage is dynamic but execessive swapping can lead to fragmentation. Also has cons such as:

• Physical wear and tear

• Less predictability

• Non-contiguous

Allows for multiple users to use the same client [disk partition → uses authentication methods to identify users]

- Assigned priority and dependencies
- Children rely on parents to execute their tasks 
- Because this version has no feedback, it will run without giving errors and can give indecipherable outputs

Computer system has more than one core, so run across multiple cores

A program is written in threads that can be executed in parallel

every program is split into multiple tasks and these tasks are split into multiple cores

Threads can’t be dependent on the same resource - leads to deadlock

The transfer of data between primary and secondary memory, done in specific amounts at a time (pages, ex:- 20mB)

ACC
ALU
CU
CIR
MDR
MDB
MAR
MAB
RAM

achieved only under ideal conditions:
- no heat
- no obstruction
- no virtual memories
- no interrupts

Processor continuously (ie present frequency) checks the peripheral devices on their status

Million instructions per second (MIPS)

NIC is responsible for the client connection to the WAN

4E

Non-volatile primary memory

CPU allocates / runs every job in a predetermined time slice, so basically splits the work of all the available into the same portions of tasks and does it at the same time. Ex. 4ms for all tasks, so it started with task 1, even if it's too much or not enough time. 

A method of compression that looks for repeating patterns and encodes them into one item of data of a specific length

The time taken, alongside fetching/waiting and executing

Static RAM:

• Does not leak

• Super fast

• Very expensive (Needs more transistors per byte)

• Used usually for cache [which stores more frequently used applications]

  • L1 <- inside CPU

  • L2 <- between CPU and primary memory

Sequence of print jobs

Average bandwidth achieved across extraneous / all confounding variables when the CPU runs

- First come first serve
- Shortest job first
- Round robin
- Multi-Level Feedback Queue
- Multi-Level Queue

False

Wait → Ready → Execute

Lossy compression and lossless compression

Peak theoretical bandwidth and sustained memory bandwidth

An extension of ASCII that adds other languages support

CPU or system

It combines different letters to create new, longer ones. Goes to UTF-8, UTF-16, UTF-32

Data can be retrieved with indexed values

Data can only be retrieved by reading all data that was sequentially stored up until that point

it's responsible for the IP and MAC addressing related to the client, whenever a connection/session is established

The 12-digit hexadecimal code is found on a network interface card.

Data processing performed on-the-fly in which the generated data influences the actual process taking place. For example” aircraft control

Data processing performed by a single processor through the use of equipment that it controls. For example: airline reservation